1. Technical Field
The present invention relates to a packet processing apparatus, in particular a packet processing apparatus to process packet data at timing based on a clock signal.
2. Background Art
As energy conservation measures have been discussed around the World for the global environmental protection, legislation and enforcement of laws aimed at energy conservation and reduction of carbon dioxide emissions have also started to be discussed in various countries. In general, the energy conservation measures tend to be perceived as measures aimed at energy consumption involved in transportation, distribution, and manufacture. However, the increase in energy consumed by information communication devices and devices related to network infrastructure, as well as electronic devices such as computers and servers has been also getting attention in recent years. Therefore, it becomes necessary to take energy conservation measures in such technical fields.
Among these devices, with regard to the electronic devices such as computers and servers, they usually have relatively long time periods during which no operations are carried out (the so-called “standby state”). It is possible to reduce the average power consumption of such electronic devices by reducing power consumption while the electronic devices are in the standby state, and thereby to make a significant contribution to the reduction of carbon dioxide emissions calculated from the average power consumption. Meanwhile, with regard to the information communication devices, although they has been converted from analog communication devices to digital communication devices, they are still required to be constantly maintained in the state capable of carrying out data communications. Therefore, in the case of information communication devices, there is a prerequisite that, unlike the electronic devices such as computers and servers, the standby state is not feasible. That is, in the case of information communication devices, it is necessary to reduce electrical power in the normal operation state to reduce the average power consumption.
Therefore, only techniques taken from a viewpoint of device technology (for example, reduction in operating voltage resulting from higher integration and miniaturization of electronic components) are in the mainstream of techniques to achieve reduction in electrical power required in the information communication devices. However, the effect of reducing operating voltage resulting from the miniaturization of electronic components has reached such a level that the operating voltage is less than one volt. Since the reduction in operating voltage has shown a tendency to slow down, the effect by the higher integration has also shown a tendency to slow down. Therefore, it has become very difficult to reduce power consumption by a large amount. Furthermore, as the miniaturization has advanced to such a level that the width of wiring lines becomes less than 90 nm (nanometer), leak currents have become so large that they can no longer be ignored. Therefore, power consumption in the standby state has been increasing even though device vendors have been conducting their own research in device technology.
Meanwhile, energy conservation measures taken from a viewpoint of circuit designs have been also studied. For example, it might be a good idea to adopt an asynchronous circuit configuration and method without using a clock as a substitute for the clock-synchronous circuit configuration and method, which is in the mainstream of circuit configurations used within design electronic components. By adopting the asynchronous circuit configuration and method, it is possible to reduce the power consumption. This technique is aimed at achieving a reducing effect on the average power consumption by reducing power consumption in the normal operation and in the standby state. However, since development tools for the designing and the verification have not been upgraded sufficiently, developers of general electronic components such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays) have no opportunity to utilize the asynchronous circuit configuration and method.
Now, a configuration example of a packet processing function of a packet communication device in which an incoming traffic capacity varies is explained hereinafter with reference to FIG. 1. In this configuration, a packet is firstly input from a packet input terminal 111 to a packet buffer F-unit 112 in synchronization with a clock input from an input clock input terminal 131. The packet is accumulated at the buffer F-unit 112. Furthermore, the packet accumulated at the packet buffer F-unit 112 is output to a packet processing A-unit 113 where a first packet process A is to be carried out. The process A is carried out on the packet at the packet processing A-unit. Furthermore, the packet for which the process A is completed at the packet processing A-unit 113 is delivered via a clock transfer D-unit 114 to a packet processing B-unit 115 where a second packet process B is to be carried out. The process B is carried out on the packet in the packet processing B-unit 115. Furthermore, the packet for which the process B is completed at the packet processing B-unit 115 is delivered via a clock transfer E-unit 116 to a packet processing C-unit 117 where a third packet process C is to be carried out. The process C is carried out on the packet in the packet processing C-unit 117. Furthermore, the packet for which the process C is completed at the packet processing C-unit 117 is delivered to a packet buffer G-unit 118, and output from the packet output terminal 119 in synchronization with a clock input from an output clock input terminal 132. Furthermore, a clock distribution unit 140 generates clocks 1, 2, and 3 having appropriate frequencies required in the respective constitutional blocks from a reference clock input from a reference clock input terminal 134. The clock distribution unit 140 supplies the generated clocks to the respective constitutional blocks.
However, in the configuration described above, intervals between input packets become larger, so that the incoming traffic capacity is lowered. Furthermore, the clocks are constantly supplied from the clock distribution unit 140 even when no packet exists in the packet processing A-unit, the packet processing B-unit, and the packet processing C-unit and thereby no packet processing operations are required. Since the clocks are constantly supplied even when packet processing is not required in any of the packet processing units, each unit consumes electrical power in a constant manner. That is, it causes power consumption called “standby power consumption” in the above-described configuration. As a result, the average operating power consumption is never reduced by a large amount even when the traffic is low, and therefore it is impossible to achieve power savings.
To deal with this problem, Japanese Unexamined Patent Application No. 2006-345278 (hereinafter called “Patent document 1”) and Japanese Unexamined Patent Application No. 2004-274099 (hereinafter called “Patent document 2”) disclose techniques in which power consumption is reduced by suspending the supply of a clock signal. Specifically, in an image processing circuit in Patent document 1, the supply of an operating clock to flip-flops that are not required to operate is suspended based on the maximum value corresponding to a value for the brightest portion in the image data. Furthermore, in Patent document 2, in a case where a constantly-operating macro and an intermittently-operating macro are arranged in series, when it is detected that no packet is output from the constantly-operating macro at the preceding stage for a certain time period, the supply of the clock to the intermittently-operating macro at the subsequent stage is suspended.
However, the technique described above cannot operate properly when the number of stages of processing-units that operate with clock signals is large. For example, packet output to a certain processing-unit is monitored in the technique of Patent document 2. However, if some processing data remains in a processing-unit for which the supply of a clock is to be suspended, that data cannot be processed. As a result, it poses a problem that the throughput of the data processing is lowered.
An exemplary object of the present invention is to reduce the power consumption without the loss of the throughput in a packet communication device in which the incoming traffic capacity varies.